Cache and store buffer maintenance in cortex-a8!
（1）、在armv7中，这些通用的系统寄存器是有两组的，即根据SCR.NS比特位的不同，会自动访问相应的那一组寄存器。 也就是说，你在linux中和在 tee 中读写的SCTLR是两个不同的寄存器; （2）、在armv8-arch64中，有SCTLR_EL1、SCTLR_EL2、SCTLR_EL3三个系统控制寄存器，这里我们只看SCTLR_EL1. 该寄存器只有一组，在双系统切换时 (linux，tee)，会在ATF代码中save/restore 该寄存器. 其实对于大多数通用的系统寄存器都是如此.
Measuring the impact of branch prediction for Cortex-R7 and Cortex-R8 ...
System control register (SCTLR) The SCTLR is another of a number of registers that are accessed using CP15, and controls standard memory, system facilities and provides status information for functions implemented in the core. The System Control Register is only accessible from PL1 or higher.
Reference - GitHub Pages
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Documentation - Arm Developer
Set this up by configuring the appropriate registers: Initialize SCTLR_EL1, System Control Register (EL1) so that El1 is in a known state. Set SPSR_EL3, Saved Program Status Register (EL3) so that the code will return to EL1 exception level.